A family of pure digital signal processing bit synchronizers

Author

Chen, Kwang-Cheng ; Lee, Jean-Ming

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

45

Issue

3

fYear

1997

fDate

3/1/1997 12:00:00 AM

Firstpage

289

Lastpage

292

Abstract

A sample-correlate-choose-largest (SCCL) algorithm is generalized to design a family of efficient baseband digital signal processing (DSP) bit synchronizers. The common feature among maximal likelihood, minimal likelihood, and zero crossing in designing SCCL type DSP bit synchronizers gives us a possible unified point of view in the general design of synchronizers. Optimal signal waveform of “+---” and “-+++” has been derived for this family of bit synchronizers under the signal bandwidth constraint of four times bit rate along with the performance analysis

Keywords

correlation methods; maximum likelihood estimation; signal sampling; signal synthesis; synchronisation; +--- waveform; -+++ waveform; DSP bit synchronizers; SCCL algorithm; bit rate; design; maximal likelihood; minimal likelihood; optimal signal waveform; performance analysis; pure digital signal processing bit synchronizers; sample-correlate-choose-largest algorithm; signal bandwidth constraint; zero crossing; AWGN; Algorithm design and analysis; Baseband; Digital signal processing; Optical signal processing; Performance analysis; Signal design; Signal processing algorithms; Timing; Tracking loops;

fLanguage

English

Journal_Title

Communications, IEEE Transactions on

Publisher

ieee

ISSN

0090-6778

Type

jour

DOI

10.1109/26.558686

Filename

558686