A simplified architecture for module (2n+1) multiplication

The module (2ⁿ+1) multiplication is widely used in the computation of convolutions and in RNS arithmetic and, thus, it is important to reduce the calculation delay. This paper presents a concept of a module (2ⁿ+1) carry save adder (MCSA) and uses two MCSAs to perform the residue reduction. We also apply Booth´s algorithm to the module (2ⁿ+1) multiplication scheme in order to reduce the number of partial products. With these techniques, the new architecture reduces the multiplier´s calculation delay and is suitable for VLSI implementation for moderate and large n (n⩾16)