• DocumentCode
    1337855
  • Title

    Unusual C – V Characteristics of High-Resistivity SOI Wafers

  • Author

    Nayak, P. ; Seacrist, M. ; Schroder, D.K.

  • Author_Institution
    Sch. of Electr., Comput. & Energy Eng., Arizona State Univ., Tempe, AZ, USA
  • Volume
    32
  • Issue
    12
  • fYear
    2011
  • Firstpage
    1659
  • Lastpage
    1661
  • Abstract
    The maximum capacitance for bulk or Silicon on Insulator (SOI) wafers is governed by the gate/contact area. During our capacitance-voltage (C-V) characterization of high-resistivity SOI wafers with Al contacts directly on the Si film, we observed the maximum capacitance to be much higher than that due to the contact area, suggesting bias spreading due to the distributed transmission line of the film resistance and buried oxide capacitance. In addition, an “S”-shape C-V plot was observed in the accumulation region.
  • Keywords
    electrical contacts; silicon-on-insulator; S-shape C-V plot; buried oxide capacitance; capacitance-voltage characterization; distributed transmission line; film resistance; gate-contact area; high-resistivity SOI wafers; silicon on insulator wafers; Area measurement; Capacitance; Doping; Logic gates; Silicon; Silicon on insulator technology; Substrates; $C$– $V$ characteristics; Bias spreading; high-resistivity SOI (HRS); low-pass filter effect; transmission-line effect;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/LED.2011.2167651
  • Filename
    6032710
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1337855