DocumentCode :
1338604
Title :
Novel clamp circuits for IC power supply protection
Author :
Maloney, Timothy J. ; Dabral, Sanjay
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Volume :
19
Issue :
3
fYear :
1996
fDate :
7/1/1996 12:00:00 AM
Firstpage :
150
Lastpage :
161
Abstract :
Biased and terminated p-n-p transistor chains are made from floating n-wells in p-substrate complementary metal-oxide semiconductor (CMOS) and used for power supply electrostatic discharge (ESD) clamps. The p-n-p gain may allow a compact termination circuit to be used, resulting in a stand-alone clamp. Bipolar p-n-p action accounts for unwanted low-voltage conduction as well as for very desirable clamping of power supply overvoltages. Bias networks are used to prevent excessive leakage at high temperature. These devices are becoming crucial to success in ESD product testing of CMOS integrated circuits
Keywords :
CMOS integrated circuits; electrostatic discharge; power supply circuits; protection; ESD product testing; IC power supply protection; bias network; clamp circuit; electrostatic discharge; floating n-wells; leakage; overvoltage; p-n-p transistor chain; p-substrate CMOS integrated circuit; termination circuit; CMOS integrated circuits; Circuit testing; Clamps; Electrostatic discharge; Integrated circuit testing; MOS devices; Power supplies; Protection; Surges; Temperature;
fLanguage :
English
Journal_Title :
Components, Packaging, and Manufacturing Technology, Part C, IEEE Transactions on
Publisher :
ieee
ISSN :
1083-4400
Type :
jour
DOI :
10.1109/3476.558861
Filename :
558861
Link To Document :
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