Title :
A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements
Author :
Pilo, Harold ; Arsovski, I. ; Batson, Kevin ; Braceras, Geordie ; Gabric, John ; Houle, Robert ; Lamphier, Steve ; Radens, Carl ; Seferagic, Adnan
Author_Institution :
IBM Syst. & Technol. Group, Essex Junction, VT, USA
Abstract :
A 64 Mb SRAM macro has been fabricated in a 32 nm high-k metal-gate SOI technology. The SRAM features a 0.154 μm2 bit-cell, the smallest to date for a 32 nm SOI product. A 0.7 V VDDMIN operation is enabled by three assist features. Stability is improved by a bit-line regulation scheme which reduces charge injection into the bit-cell. Enhancements to the write path include an increase of 40% of bit-line boost voltage. Finally, a bit-cell-tracking delay circuit improves both performance and yield across the process space.
Keywords :
SRAM chips; circuit stability; silicon-on-insulator; SRAM; bit-cell-tracking delay circuit; byte rate 64 MByte/s; high-k metal-gate SOI technology; read-ability; size 32 nm; stability; voltage 0.7 V; write-ability; Circuit stability; Logic gates; Random access memory; Regulators; Stability analysis; Thermal stability; Voltage control; 32 nm; CMOS memory integrated circuits; Vddmin; high-k metal-gate; read assist; stability assist; static random-access memory (SRAM); write assist;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2011.2164730
