DocumentCode
1339065
Title
Fast Carry Logic for Digital Computers
Author
Gilchrist, Bruce ; Pomerene, J.H. ; Wong, S.Y.
Author_Institution
Institute for Advanced Study, Princeton, N. J.
Issue
4
fYear
1955
Firstpage
133
Lastpage
136
Abstract
Existing large scale binary computers typically must allow for the maximum full length carry time in each addition. It has been shown that average carry sequences are significantly shorter than this maximum, on the average only five stages for a 40 digit addition. A method is described to realize the implied 8 to 1 time saving by deriving an actual ``carry completion´´ signal. Experimental results verify this saving.
Keywords
Adders; Arithmetic; Large-scale systems; Logic circuits; Logic design; Safety devices; Timing;
fLanguage
English
Journal_Title
Electronic Computers, IRE Transactions on
Publisher
ieee
ISSN
0367-9950
Type
jour
DOI
10.1109/TEC.1955.5219482
Filename
5219482
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