A simple and efficient measurement method for characterizing capacitance matrix of multilayer interconnection in VLSI

Author

Mido, Tetsuhisa ; Ito, Hiroshi ; Asada, Kunihiro

Author_Institution

VLSI Design & Educ. Center, Tokyo Univ., Japan

Volume

13

Issue

2

fYear

2000

fDate

5/1/2000 12:00:00 AM

Firstpage

145

Lastpage

151

Abstract

A compact new test structure for direct extraction of components of the capacitance matrix for multilayer interconnections is presented. In this new method, each capacitive component in integrated structures is separately and directly obtained from measurement, and the total pads are kept to eight, independent of the size of the target matrix. As a result of evaluation of measurement errors caused by the asymmetry of structures, this new method can measure components of capacitance matrix with a precision of femto-farad order

Keywords

VLSI; capacitance measurement; integrated circuit interconnections; integrated circuit measurement; measurement errors; VLSI; asymmetry; capacitance matrix; direct extraction; femto-farad precision; measurement errors; measurement method; multilayer interconnection; target matrix; total pads; Capacitance measurement; Circuit testing; Data mining; Delay estimation; Driver circuits; Indium tin oxide; Integrated circuit interconnections; Nonhomogeneous media; Parasitic capacitance; Very large scale integration;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/66.843629

Filename

843629