Title :
Adaptive-biased buffer with low input capacitance
Author :
Chan, P.K. ; Siek, L. ; Lim, T. ; Han, M.K.
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore
fDate :
4/27/2000 12:00:00 AM
Abstract :
A new analogue buffer, which is a differential-pair-based level shifter followed by an adaptive-biased cascode source follower, is proposed. The structure exhibits low input capacitances, enhanced slew rate, high bandwidth and low distortion. The simulated results have shown input capacitance of 99.5 fF at 1 MHz, slew rate of 55.5 V/μs, -3 dB bandwidth of 37.9 MHz, and THD less than 1% for 1 Vpp input signal up to 6 MHz at a 100 kΩ//15 pF load. The buffer consumes 2.4 mW at 5 V supply in a 0.8 μm n-well CMOS technology
Keywords :
CMOS analogue integrated circuits; buffer circuits; capacitance; 0.8 micron; 2.4 mW; 37.9 MHz; 5 V; 99.5 fF; adaptive-biased buffer; adaptive-biased cascode source follower; analogue buffer; differential-pair-based level shifter; high bandwidth; low distortion; low input capacitance; n-well CMOS technology; slew rate enhancement;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20000644
