• DocumentCode
    1339870
  • Title

    Bit rate and protocol independent clock and data recovery

  • Author

    Stilling, B.

  • Author_Institution
    Inf. & Commun. Networks, Siemens AG, Munich, Germany
  • Volume
    36
  • Issue
    9
  • fYear
    2000
  • fDate
    4/27/2000 12:00:00 AM
  • Firstpage
    824
  • Lastpage
    825
  • Abstract
    A design for a bit rate and protocol independent clock and data recovery circuit (CDRC) for use in optoelectronic regenerators is presented. A conventional phase-locked loop (PLL) has been extended to a combined phase/frequency-locked loop by adding two additional frequency detectors (FDs). This architecture guarantees reliable clock synchronisation of the input data with different line codes over a frequency range spanning multiple octaves
  • Keywords
    optical repeaters; phase locked loops; synchronisation; bit rate; clock and data recovery circuit; frequency detector; frequency locked loop; optoelectronic regenerator; phase locked loop; protocol; synchronisation;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20000603
  • Filename
    843796
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1339870