DocumentCode
1340312
Title
Power estimation of digital data paths using HEAT
Author
Satyanarayana, Janardhan H. ; Parhi, Keshab K.
Author_Institution
Lucent Technol., Bell Labs., Holmdel, NJ, USA
Volume
17
Issue
2
fYear
2000
Firstpage
101
Lastpage
110
Abstract
The major concerns of VLSI designers in the past were performance, area, reliability and cost. Power was only a secondary issue. In recent years, however, power, area, and speed have become equally important. There are many reasons for this new trend. Primarily, rapid advancement in semiconductor technology over the past decade has enabled designers to integrate many digital CMOS circuits on a single chip. However, the desirability of using these circuits in portable operations has necessitated the development of low-power technology. Portable applications range from desktop computers and audio-video based multimedia products to personal digital assistants and personal communicators. These systems demand both complex functionality and low power, which make their design challenging. The hierarchical energy analysis tool lets designers quickly estimate power consumption of various data-path architectures, enabling a power consumption comparison at a high level before the layout design is carried out
Keywords
VLSI; circuit CAD; power consumption; HEAT; VLSI designers; data-path architectures; digital CMOS circuits; digital data paths; hierarchical energy analysis tool; multimedia products; personal communicators; personal digital assistants; power estimation; semiconductor technology; Application software; CMOS digital integrated circuits; CMOS technology; Costs; Energy consumption; Integrated circuit reliability; Personal digital assistants; Portable computers; Very large scale integration; Videos;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/54.844339
Filename
844339
Link To Document