M-PRES: a statistical tool for modelling the impact of manufacturing process variations on circuit-level performance parameters

Author

Shedabale, S. ; Russell, G. ; Yakovlev, Alex

Author_Institution

Sch. of Electr., Electron. & Comput. Eng., Newcastle Univ., Newcastle upon Tyne, UK

Volume

5

Issue

5

fYear

2011

fDate

9/1/2011 12:00:00 AM

Firstpage

403

Lastpage

410

Abstract

The effects of process variations on the performance of nanometre CMOS circuits have become a serious design issue, aggravated by further scaling of device dimensions. This article presents a statistical TCAD tool called Multilevel-Partitioned REsponse Surface Modelling (M-PRES) to model the impact of manufacturing process variations on circuit performance; an SRAM cell is used as a demonstration vehicle for the tool. A new non-Gaussian approach for modelling variations for sub-90 nm technologies is also presented. A comparison is made with the Monte Carlo approach, demonstrating four times (4×) computationally efficiency for M-PRES without the loss of accuracy. The M-PRES models are also re-usable reducing the computation time for the analysis of other sets of process data down to a few tens of seconds.

Keywords

CMOS memory circuits; Monte Carlo methods; SRAM chips; manufacturing processes; technology CAD (electronics); M-PRES; Monte Carlo approach; SRAM cell; circuit-level performance parameters; manufacturing process variations; multilevel-partitioned response surface modelling; nanometre CMOS circuits; nonGaussian approach; scaling; size 90 nm; statistical TCAD tool;

fLanguage

English

Journal_Title

Circuits, Devices & Systems, IET

Publisher

iet

ISSN

1751-858X

Type

jour

DOI

10.1049/iet-cds.2010.0110

Filename

6034869