Title :
Fault coverage and defect level estimation models for partially testable MCMs
Author :
Tseng, W.-D. ; Wang, K.
Author_Institution :
Dept. of Comput. & Inf. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
4/1/2000 12:00:00 AM
Abstract :
The authors propose a simple and efficient mathematical model for designers to estimate fault coverage for partially testable multichip modules (MCMs). This model shows a relation between fault coverage, test methodology, and the fraction and distribution of design for testability (DFT) dies in MCMs. Experimental results show that the proposed model can efficiently predict the fault coverage of a partially testable MCM with less than 5% deviation. An automatic DFT dies deployment algorithm, based on the genetic algorithm and the model is proposed to help designers to obtain a fault coverage as close to the upper bound of fault coverage as possible. Two defect level estimation models, which relate fault coverage and manufacturing yield for measuring the test quality of MCMs under equiprobable and non-equiprobable faults, respectively are also formulated and analysed to support the effectiveness of the model
Keywords :
design for testability; genetic algorithms; integrated circuit design; integrated circuit modelling; integrated circuit testing; multichip modules; defect level; design for testability; die deployment automation; estimation model; fault coverage; genetic algorithm; manufacturing yield; multichip module; partially testable MCM;
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings -
DOI :
10.1049/ip-cds:20000198