• DocumentCode
    1340852
  • Title

    Transistor operation of 30-nm gate-length EJ-MOSFETs

  • Author

    Hawaura, H. ; Sakamoto, T. ; Baba, T. ; Ochiai, Y. ; Fujita, J. ; Matsui, S. ; Sone, J.

  • Author_Institution
    NEC Fundamental Res. Labs., Ibaraki, Japan
  • Volume
    19
  • Issue
    3
  • fYear
    1998
  • fDate
    3/1/1998 12:00:00 AM
  • Firstpage
    74
  • Lastpage
    76
  • Abstract
    We have fabricated electrically variable shallow junction metal-oxide-silicon field-effect transistors (EJ-MOSFET´s) to investigate transistor characteristics of ultrafine-gate MOSFET´s. By using EB direct writing onto an ultrahigh-resolution negative resist (calixarene), we achieved a gate length of 32 nm for the first time. The short-channel effects were effectively suppressed by electrically induced ultrashallow source/drain regions, and the fabricated device exhibited normal transistor characteristics even in the 32-nm gate-length regime at room temperature: an ON/OFF current ratio of 105 and a cut-off current of 20 pA/μm.
  • Keywords
    MOSFET; electron beam lithography; 30 nm; EB direct writing; EJ-MOSFET; ON/OFF current ratio; calixarene; cut-off current; electrically variable shallow junction metal-oxide-silicon field-effect transistor; gate length; short-channel effect; ultrafine-gate MOSFET; ultrahigh-resolution negative resist; ultrashallow source/drain region; Degradation; Doping; FETs; MOSFET circuits; Project management; Research and development management; Resists; Temperature; Voltage; Writing;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/55.661169
  • Filename
    661169