Automated low-power technique exploiting multiple supply voltages applied to a media processor

Author

Usami, Kimiyoshi ; Igarashi, Mutsunori ; Minami, Fumihiro ; Ishikawa, Takashi ; Kanzawa, M. ; Ichida, Makoto ; Nogami, Kazutaka

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

33

Issue

3

fYear

1998

fDate

3/1/1998 12:00:00 AM

Firstpage

463

Lastpage

472

Abstract

This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement, and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced voltage or the unreduced one to each row so as to minimize the area overhead. The reduced supply, voltage is also exploited in a clock tree to reduce power. Combining these techniques together, we applied it to a media processor chip. The combined technique reduced the power by 47% in random-logic modules and by 73% in the clock tree, while keeping the performance

Keywords

CMOS digital integrated circuits; circuit layout CAD; high level synthesis; integrated circuit layout; microprocessor chips; network routing; timing; automated design technique; automated low-power technique; clock tree; media processor chip; multiple supply voltages; placement; random-logic modules; routing; structure synthesis; Circuit synthesis; Clocks; Degradation; Delay; Design automation; Leakage current; Logic circuits; Routing; Timing; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.661212

Filename

661212