A stochastic wire-length distribution for gigascale integration (GSI). II. Applications to clock frequency, power dissipation, and chip size estimation

Author

Davis, Jeffrey A. ; De, Vivek K. ; Meindl, James D.

Author_Institution

Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA

Volume

45

Issue

3

fYear

1998

fDate

3/1/1998 12:00:00 AM

Firstpage

590

Lastpage

597

Abstract

For pt.I see ibid., vol.45, no.3, pp.580-9 (Mar. 1998). Based on Rent´s Rule, a well-established empirical relationship, a complete wire-length distribution for on-chip random logic networks is used to enhance a critical path model; to derive a preliminary dynamic power dissipation model; and to describe optimal architectures for multilevel wiring networks that provide maximum interconnect density and minimum chip size

Keywords

integrated circuit interconnections; integrated circuit modelling; integrated logic circuits; stochastic processes; GSI; Rent´s Rule; chip size; clock frequency; critical path model; dynamic power dissipation model; gigascale integration; interconnect density; multilevel wiring network architecture; on-chip random logic network; stochastic wire length distribution; Clocks; Delay effects; Frequency estimation; Integrated circuit interconnections; Life estimation; Power dissipation; Power system modeling; Semiconductor device modeling; Stochastic processes; Wiring;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.661220

Filename

661220