New Delay-Time Measurements on a 64-kb Josephson–CMOS Hybrid Memory With a 600-ps Access Time

A 64-kb subnanosecond Josephson-CMOS hybrid random-access memory (RAM) has been developed with ultrafast hybrid interface circuits. The hybrid memory is designed and fabricated using a commercial 0.18-??m CMOS process and NEC-SRL´s 2.5- kA/cm² Nb process for Josephson circuits. The millivolt-level Josephson signals are amplified to volt-level CMOS digital signals by a hybrid interface amplifier, which is the most challenging part of the memory system. The performance of this amplifier is optimized by minimizing its parasitic capacitance loading. The 4-K operation of short-channel CMOS devices and circuits is reviewed, and a complete 4-K CMOS BSIM3 model, which has been verified by experiments, is discussed. The memory bit-line output currents are detected by ultralow-power high-speed Josephson devices. Here, we report the first high-frequency access-time measurements on the full critical path showing 600 ps for a single bit. We discuss future designs made to reduce the crosstalk and improve margins, as well as plans to reduce power dissipation and latency.