Fault Modeling and Worst-Case Test Vectors for Delay Failures Induced by Total Dose in ASICs

We analyzed the delay failure induced in standard-cell ASICs by total-ionizing dose. We developed a novel cell-level fault model for delay failures. We used this fault model to identify worst-case test vectors (WCTV) for delay failures induced in ASIC devices exposed to total ionizing dose. The fault model was experimentally validated using SPICE simulation and total dose data. We introduced a fast search algorithm based on directed graph and genetic algorithms to help identify WCTV for large ASICs within reasonable search time. The methodology was validated using ASIC test chip and Cobalt 60 facility.