Title :
Efficient retiming of large circuits
Author :
Maheshwari, Naresh ; Sapatnekar, Sachin
Author_Institution :
Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
fDate :
3/1/1998 12:00:00 AM
Abstract :
Retiming, introduced by Leiserson and Saxe (1983, 1991), is a powerful transformation of circuits that preserves functionality and improves performance. The ASTRA algorithm proposed an alternative view of retiming using the equivalence between retiming and clock skew optimization and also presented a fast algorithm for minimum period (minperiod) retiming. Since minperiod retiming may significantly increase the number of flip-flops in the circuit, minimum area (minarea) retiming is an important problem. Minarea retiming is a much harder problem than minperiod retiming, and previous techniques were not capable of handling large circuits in a reasonable time. This work defines the relationship between the Leiserson-Saxe and the ASTRA approaches and utilizes it for efficient minarea retiming of large circuits. The new algorithm, Minaret, uses the same basis as the Leiserson-Saxe approach. The underlying philosophy of the ASTRA approach is incorporated to reduce the number of variables and constraints generated in the problem. This allows minarea retiming of circuits with over 56 000 gates in under 15 min.
Keywords :
VLSI; circuit layout CAD; circuit optimisation; digital integrated circuits; integrated circuit layout; integrated logic circuits; linear programming; logic CAD; sequential circuits; timing; ASTRA algorithm; Leiserson-Saxe approach; Minaret algorithm; clock skew optimization; large circuits; minimum area retiming; minimum period retiming; retiming algorithms; Circuit optimization; Circuit synthesis; Clocks; Design automation; Flip-flops; Linear programming; Logic design; Logic programming; Sequential circuits; Very large scale integration;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on