DocumentCode :
1341404
Title :
SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design
Author :
Gajski, Daniel D. ; Vahid, Frank ; Narayan, Sanjiv ; Gong, Jie
Author_Institution :
Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
Volume :
6
Issue :
1
fYear :
1998
fDate :
3/1/1998 12:00:00 AM
Firstpage :
84
Lastpage :
100
Abstract :
System-level design issues are gaining increasing attention, as behavioral synthesis tools and methodologies mature. We present the SpecSyn system-level design environment, which supports the new specify-explore-refine (SER) design paradigm. This three-step approach to design includes precise specification of system functionality, rapid exploration of numerous system-level design options, and refinement of the specification into one reflecting the chosen option. A system-level design option consists of an allocation of system components, such as standard and custom processors, memories, and buses, and a partitioning of functionality among those components. After refinement, the functionality assigned to each component can then he synthesized to hardware or compiled to software. We describe the issues and approaches for each part of the SpecSyn environment. The new paradigm and environment are expected to lead to a more than ten times reduction in design time, and our experiments support this expectation.
Keywords :
VLSI; circuit CAD; digital integrated circuits; high level synthesis; integrated circuit design; real-time systems; SpecSyn; design time reduction; functionality partitioning; hardware/software codesign; hardware/software system design; specify-explore-refine paradigm; system components allocation; system-level design environment; three-step design approach; Application specific integrated circuits; Computer science; Embedded software; Embedded system; Hardware; Integrated circuit interconnections; Software design; Software systems; System-level design;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/92.661251
Filename :
661251
Link To Document :
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