One-pass assembler design for a low-end reconfigurable RISC processor

Implementation of processor core on a programmable device such as Field Programmable Gate Array (FPGA) has been widely adopted by researchers due to its flexibility and hardware reconfigurability. However, with processor design is a tightly integrated development of hardware and software, changes in the processor´s hardware architecture would require the same alterations being made on the software side. This paper presents a one-pass assembler design technique that adapts to modifications of the instruction set architecture (ISA) on a reconfigurable processor. A Reduced Instruction Set Computer (RISC) processor core, which is described in Verilog Hardware Description Language (HDL), is used as the testing platform whereby its ISA is expanded to perform the instruction set extension. A lexical analyzer and tokenization technique is adopted in the assembler development with several hash tables are setup to store all the tokens. The assembler would generate a coefficient file that contained all the translated instruction codes sourced from an assembly program. The coefficient file then is initiated in the memory module of the RISC processor core using Xilinx Spartan-3AN FPGA board. Based on the simulation results, the assemblers have been successfully developed with working coefficient file output format that matched to the ISA modifications.