Critical area extraction for soft fault estimation

Author

Allan, Gerard A. ; Walton, Anthony J.

Author_Institution

Dept. of Electr. Eng., Edinburgh Univ., UK

Volume

11

Issue

1

fYear

1998

fDate

2/1/1998 12:00:00 AM

Firstpage

146

Lastpage

154

Abstract

Algorithms are presented for extracting the critical area associated with extra and missing material soft faults of an integrated circuit from the mask layout. These algorithms have been implemented within the Edinburgh Yield Estimator (EYE) tool which permits efficient extraction of the critical area from an arbitrary mask layout. Accurate estimates of device critical area of even the largest devices can be obtained in a reasonable time using the sampling version of the tool. The application of these algorithms to defect related reliability is explored and results reported that compare the susceptibility to soft faults before and after layout modifications intended to enhance manufacturing yield. These results suggest that yield enhancement techniques can have a significant impact on defect-related device reliability

Keywords

VLSI; circuit layout CAD; fault diagnosis; integrated circuit layout; integrated circuit reliability; integrated circuit yield; masks; reliability theory; EYE tool; Edinburgh Yield Estimator tool; critical area extraction; defect related reliability; device critical area estimation; integrated circuit; layout modifications; manufacturing yield; mask layout; sampling version; soft fault estimation; yield enhancement techniques; Circuit faults; Circuit testing; Helium; Integrated circuit layout; Integrated circuit reliability; Integrated circuit yield; Manufacturing; Sampling methods; Very large scale integration; Yield estimation;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/66.661294

Filename

661294