• DocumentCode
    1341828
  • Title

    Low-noise wideband PLL with dual-mode ring-VCO

  • Author

    Lee, Hwi Don ; Yun, S.-J. ; Kim, K.-D. ; Kwon, J.-K.

  • Author_Institution
    Electron. & Telecommun. Res. Inst., Daejeon, South Korea
  • Volume
    46
  • Issue
    20
  • fYear
    2010
  • Firstpage
    1368
  • Lastpage
    1370
  • Abstract
    A low-jitter 110 MHz-to-620 MHz phase-locked loop (PLL) that includes a low-noise wide-frequency-range ring oscillator with a dual-mode operation is presented. The measurement results using a 65 nm low-power CMOS process show that the proposed PLL achieves as low as a 2.5 ps RMS jitter at 600 MHz of output frequency while consuming 2.7 mW at a 1.2 V supply. The die area is only 0.09 mm2.
  • Keywords
    CMOS integrated circuits; UHF oscillators; VHF oscillators; jitter; low-power electronics; phase locked loops; voltage-controlled oscillators; dual-mode ring-VCO; frequency 110 MHz to 620 MHz; low-jitter phase locked loop; low-noise wideband PLL; low-power CMOS process; power 2.7 mW; size 65 nm; voltage 1.2 V; wide-frequency-range ring oscillator;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el.2010.2028
  • Filename
    5593955
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1341828