• DocumentCode
    1342326
  • Title

    STBM: a fast algorithm to simulate IDDQ tests for leakage faults

  • Author

    Chakravarty, Sreejit ; Zachariah, Sujit Thomas

  • Author_Institution
    Test Technol., Intel Corp., Santa Clara, CA, USA
  • Volume
    19
  • Issue
    5
  • fYear
    2000
  • fDate
    5/1/2000 12:00:00 AM
  • Firstpage
    568
  • Lastpage
    576
  • Abstract
    State-transition-based method (STBM), a fast algorithm for computing leakage fault coverage of IDDQ tests and selecting optimal IDDQ measurement points, targeting leakage faults, is presented. Experimental results presented show that STBM outperforms all known algorithms for the same problems. A comparative study of leakage and pseudo-stuck-at fault models, the latter used by commercial tool vendors, show that the pseudo-stuck-at coverage values are very pessimistic
  • Keywords
    CMOS digital integrated circuits; digital simulation; electronic engineering computing; fault simulation; integrated circuit testing; leakage currents; logic testing; IDDQ tests simulation; STBM algorithm; fast algorithm; fault currents; leakage faults; optimal IDDQ measurement points selection; state-transition-based method; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Fault currents; Fault diagnosis; Logic testing; Microprocessors; Semiconductor device testing; Sequential circuits;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.845081
  • Filename
    845081
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1342326