Title :
Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications
Author :
Djahanshahi, Hormoz ; Salama, C. André T
Author_Institution :
PMC-Sierra Inc., Burnaby, BC, Canada
fDate :
6/1/2000 12:00:00 AM
Abstract :
This paper describes the architecture and components of a high-speed clock and data recovery (CDR) circuit. Fully differential CMOS circuits are presented for an integrated physical layer controller of a 622-Mb/s (OC-12) system, although the design can be used in other systems with clock speeds in the 622-933-MHz range. Simulations and experimental results are presented for the building blocks including novel designs for a current-controlled oscillator (CCO) and a differential charge pump. The CCO is based on a two-stage ring oscillator. It consists of parallel differential amplifier pairs which reliably generate the necessary phase shift and gain to fulfill the oscillation conditions over process and temperature variations. Two test chips are implemented in 0.35-/spl mu/m CMOS. One contains partitioned building blocks of a phase-locked loop (PLL) which, together with an external loop filter, can be used for flexible testing and CDR applications. The other chip is a monolithic CDR with integrated loop filter. It exhibits a power consumption of 0.2 W and a measured rms clock jitter of 12.5 ps at 933 MHz.
Keywords :
CMOS integrated circuits; clocks; differential amplifiers; mixed analogue-digital integrated circuits; phase locked loops; synchronisation; timing jitter; 0.2 W; 0.35 micron; 622 MHz; 933 MHz; CDR applications; PLL; current-controlled oscillator; data recovery applications; differential CMOS circuits; differential charge pump; high-speed clock; integrated physical layer controller; loop filter; oscillation conditions; parallel differential amplifier pairs; partitioned building blocks; power consumption; rms clock jitter; temperature variations; two-stage ring oscillator; Charge pumps; Circuit simulation; Clocks; Control systems; Differential amplifiers; Filters; Phase locked loops; Physical layer; Ring oscillators; Testing;
Journal_Title :
Solid-State Circuits, IEEE Journal of