Single-Event Transient Pulse Quenching in Advanced CMOS Logic Circuits

Author

Ahlbin, Jonathan R. ; Massengill, Lloyd W. ; Bhuva, Bharat L. ; Narasimham, Balaji ; Gadlage, Matthew J. ; Eaton, Paul H.

Author_Institution

Vanderbilt Univ., Nashville, TN, USA

Volume

56

Issue

6

fYear

2009

Firstpage

3050

Lastpage

3056

Abstract

Heavy-ion broad-beam experiments on a 130 nm CMOS technology have shown anomalously-short single-event transient pulse widths. 3-D TCAD mixed-mode modeling in 90 nm and 130 nm bulk CMOS has identified a mechanism for simultaneous charge collection on proximal circuit nodes interacting in a way as to truncate, or Â¿quench,Â¿ a propagated voltage transient, effectively limiting the observed SET pulse widths at high LET. This quenching mechanism is described and analyzed.

Keywords

CMOS logic circuits; technology CAD (electronics); 3D TCAD mixed-mode modeling; CMOS logic circuits; LET; charge collection; heavy-ion broad-beam experiments; proximal circuit nodes; short single-event transient pulse widths; single-event transient pulse quenching mechanism; CMOS logic circuits; CMOS technology; Logic gates; Logic testing; Microelectronics; Pulse amplifiers; Pulse circuits; Space vector pulse width modulation; Transistors; Voltage; Charge sharing; pulse quenching; single-event; single-event transient; single-event upset;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2009.2033689

Filename

5341415