SEU-Susceptibility of Logical Constants in Xilinx FPGA Designs

Author

Quinn, Heather ; Allen, Gregory R. ; Swift, Gary M. ; Tseng, Chen Wei ; Graham, Paul S. ; Morgan, Keith Shearl ; Ostler, Patrick

Author_Institution

ISR-3 Space Data Syst., Los Alamos Nat. Lab., Los Alamos, NM, USA

Volume

56

Issue

6

fYear

2009

Firstpage

3527

Lastpage

3533

Abstract

In Xilinx Field Programmable Gate Arrays two types of logical constants, implicit and explicit, are used to prevent unspecified signals from floating. Implicit logical constants are implemented with a weak keeper circuit, called a half latch, and are used to tie off unspecified input signals to user flip-flops. Explicit logical constants in the earlier devices are implemented using look up tables (LUTs) set to a constant value (constant LUTs) and in the newer devices are implemented using posts that provide access to the ground plane. Explicit logical constants often are used in adders and multipliers. In this paper, we will present radiation test data and analysis of the three types of logical constants.

Keywords

adders; field programmable gate arrays; flip-flops; logic design; radiation hardening (electronics); reliability; LUT; SEU-susceptibility; Xilinx FPGA design; Xilinx field programmable gate array; adders; flip-flops; latches; logical constant; look up table; multipliers; radiation test data; reliability; single-event upset; weak keeper circuit; Circuit testing; Clocks; Field programmable gate arrays; Flip-flops; Laboratories; Latches; Programmable logic arrays; Signal design; Single event transient; Table lookup; Fault tolerance; field programmable gate arrays; proton radiation effects; reliability estimation;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2009.2033925

Filename

5341417