A parallel architecture for multilevel decision feedback equalization

The data rate in a decision-feedback detector is limited by the critical timing loop. Within one clock cycle, the result of a decision by the comparator must be able to make its way back through the feedback filter and summing junction to reappear at the comparator input. It is shown here that multilevel decision feedback equalization (MDFE) can be readily modified to allow two clock cycles for the completion of this critical timing loop. This is accomplished by readjusting the forward equalizer until the first coefficient in the feedback filter is forced to zero. There is no significant degradation in performance in the application as a read/write channel for a hard disk drive. A parallel architecture can then be developed in which the entire structure is clocked at one half of the channel clock rate. A mixed analog/digital circuit topology is suggested for implementing this structure. A further proposal is that the feedback filter can be implemented as a set of small lookup tables, each pipelined to achieve highest data rate