Title :
Digitally Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference
Author :
Ru, Zhiyu ; Moseley, Niels A. ; Klumperink, Eric A M ; Nauta, Bram
Author_Institution :
Dept. of Electr. Eng., Univ. of Twente, Enschede, Netherlands
Abstract :
A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative ¿iterative¿ harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF, and + 3.5 dBm in-band IIP3 while the out-of-band IIP3 is +16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order HR > 60 dB over 40 chips, while the digital AIC technique achieves HR > 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply.
Keywords :
CMOS integrated circuits; harmonics suppression; interference suppression; iterative methods; low-pass filters; radio receivers; radiofrequency interference; software radio; CMOS technique; adaptive interference cancelling; analog two-stage polyphase HR concept; current 50 mA; digital AIC technique; digitally enhanced SDR receiver; frequency 0.8 GHz; gain 34 dB; harmonic mixing; iterative harmonic-rejection technique; low-pass filtering; multiphase clock generator; out-of-band interference; size 65 nm; software-defined radio; voltage 1.2 V; Baseband; Clocks; Interference; Low pass filters; Power harmonic filters; Radio frequency; Radiofrequency identification; Receivers; Robustness; Voltage; Adaptive interference cancellation; CMOS; LMS; SAW-less; adaptive signal processing; baseband processing; blocker; blocker filtering; cross-correlation; digitally assisted; digitally enhanced; harmonic mixing; harmonic rejection; interference mitigation; linearity; low-noise amplifier (LNA); low-noise transconductance amplifier (LNTA); mismatch; multiphase; multiphase clock; nonlinearity; out-of-band interference; passive mixer; polyphase; receiver; robust receiver; software radio (SWR); software-defined radio (SDR); switching mixer; wideband receiver;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2009.2032272