A 2-mm $^{2}$ 0.1–5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS

A software-defined radio (SDR) should theoretically receive any modulated frequency channel in the (un)licensed spectrum, and guarantee top performance with energy savings, while still being integrated in a digital CMOS technology. This paper demonstrates a practical 0.1-5 GHz front-end implementation for such an SDR concept, including receiver and local oscillator (LO), with only 2-mm² core area occupation in a 45-nm CMOS process. This scalable radio uses shunt-shunt feedback LNAs, a passive mixer with enhanced out-of-band IIP3, and a fifth order low-area 0.5-20 MHz baseband filter. LO quadrature signals are generated from a dual-VCO 4-10 GHz fractional-N PLL. With noise figure between 2.3 dB and 6.5 dB, out-of-band IIP3 between -3 dBm and -10 dBm, and total power consumption between 59 and 115 mW from a 1.1-V supply voltage, the presented prototype favorably compares with state-of-the-art dedicated radios while enabling, for the first time, wideband reconfigurable performance and energy scalability.