DocumentCode :
1343995
Title :
The arithmetic Fourier transform
Author :
Sadasiv, G.
Author_Institution :
Dept. of Electr. Eng., Rhode Island Univ., RI, USA
Volume :
5
Issue :
1
fYear :
1988
Firstpage :
13
Lastpage :
17
Abstract :
Preliminary results are presented on the VLSI design and implementation of a novel algorithm for accurate high-speed Fourier analysis and synthesis. The arithmetic Fourier transform (AFT) is based on the number-theoretic method of Mobius inversion. Its computations proceed in parallel, and the individual operations are very simple. Except for a small number of scalings in one state of the computation, only multiplications by 0, +1, and -1 are required. If the input samples were not quantized and if ideal real-number operations were used internally, then the results would be exact. The accuracy of the computation is limited only by the input A/D (analog-to-digital) conversion process, any constraints on the word lengths of internal accumulating registers, and the implementation of the few scaling operations. Further simplifications are obtained by using delta modulation to represent the input function in digital form, so that only binary (or preferably, ternary) sequences needs to be processed in the parallel computations. The required accumulations can be replaced by up/down counters. The dynamic range of the resulting transformation can be increased by the use of adaptive delta modulation.<>
Keywords :
Fourier transforms; signal processing; Mobius inversion; VLSI; adaptive delta modulation; arithmetic Fourier transform; internal accumulating registers; number-theoretic; scalings; signal processing; Adaptive signal processing; Algorithm design and analysis; Arithmetic; Concurrent computing; Delta modulation; Fourier transforms; Registers; Signal processing; Signal processing algorithms; Very large scale integration;
fLanguage :
English
Journal_Title :
ASSP Magazine, IEEE
Publisher :
ieee
ISSN :
0740-7467
Type :
jour
DOI :
10.1109/53.662
Filename :
662
Link To Document :
بازگشت