DocumentCode
1344803
Title
A method for increasing the IDDQ testability
Author
Dalpasso, Marcello ; Favalli, Michele
Author_Institution
Dipt. di Ingegneria, Ferrara Univ., Italy
Volume
16
Issue
10
fYear
1997
fDate
10/1/1997 12:00:00 AM
Firstpage
1186
Lastpage
1188
Abstract
At different design levels, testability is becoming more and more important since high levels of reliability are required by many applications. In this work, a novel approach to the mapping between signal lines and gate inputs is proposed, targeting the IDDQ testability of internal faults. Suggesting an additional cost function for the routing process, the method provides significant testability enhancements without affecting either the gate-level structure of the circuit or the internal layout of the gates, as proved with regards to bridging faults
Keywords
CMOS logic circuits; design for testability; integrated circuit design; integrated circuit reliability; integrated circuit testing; logic testing; CMOS logic; IDDQ testability; bridging faults; cost function; gate inputs; gate-level structure; internal faults; internal layout; mapping; reliability; signal lines; Benchmark testing; Circuit faults; Circuit testing; Cost function; Electrical fault detection; Fault detection; Integrated circuit testing; Logic design; Logic testing; Routing;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.662679
Filename
662679
Link To Document