A 0.1-μm delta-doped MOSFET fabricated with post-low-energy implanting selective epitaxy

Author

Noda, Kenji ; Tatsumi, Toru ; Uchida, Tetsuya ; Nakajima, Ken ; Miyamoto, Hidenobu ; Hu, Chenming

Author_Institution

Memory Device Dev. Lab., NEC Corp., Kanagawa, Japan

Volume

45

Issue

4

fYear

1998

fDate

4/1/1998 12:00:00 AM

Firstpage

809

Lastpage

814

Abstract

A simple fabrication technology for delta-doped MOSFETs, named post-low-energy implanting selective epitaxy (PLISE) is presented. The PLISE technology needs no additional photo-lithography mask, deposition step or etching step even for CMOS devices. The only additional step is growing undoped epitaxial channel layers by UHV-CVD after the channel implantation. With this technology, delta-doped NMOSFETs with 0.1-μm gate length were successfully fabricated. By optimizing the epi-layer thickness and the channel doping level, short-channel effects are suppressed enough to achieve 0.1-μm gate length. Moreover, the junction capacitance at zero bias is reduced by 50%

Keywords

MOSFET; capacitance; doping profiles; elemental semiconductors; ion implantation; semiconductor growth; silicon; vapour phase epitaxial growth; 0.1 micron; PLISE; Si; UHV-CVD; delta-doped MOSFET; epi-layer thickness; junction capacitance; post-low-energy implanting selective epitaxy; short-channel effects; undoped epitaxial channel layers; CMOS process; CMOS technology; Capacitance; Doping; Epitaxial growth; Fabrication; Impurities; Isolation technology; MOSFET circuits; Threshold voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.662780

Filename

662780