DocumentCode
1346083
Title
Impact of Highly Compressive Interlayer-Dielectric-
Stressing Layer on
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<Author
Chen, Yu-Ting ; Chen, Kun-Ming ; Liao, Wen-Shiang ; Huang, Guo-Wei ; Huang, Fon-Shan
Author_Institution
Inst. of Electron. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Volume
31
Issue
12
fYear
2010
Firstpage
1368
Lastpage
1370
Abstract
The 1/f noise and reliability of SiGe-channel pMOSFETs with a highly compressive contact-etching stop-layer (CESL) interlayer-dielectric-SiNx, stressing layer have been studied in this letter. The SiGe-channel devices with a highly compressive CESL layer have higher drain current and lower 1/f noise than the conventional SiGe-channel and bulk-Si devices. However, the device reliability is degraded while integrating with the highly compressive CESL layer. By examining the effective oxide-trap densities under hot-carrier instability stress, we find that the incorporated hydrogen in gate oxide during CESL layer deposition may play an important role on the 1/f noise and device reliability.
Keywords
Ge-Si alloys; MOSFET; semiconductor device reliability; SiGe channel device; compressive contact-etching stop-layer; device reliability; drain current; hot-carrier instability stress; oxide-trap density; pMOSFET reliability; Etching; Logic gates; MOSFETs; Reliability; Silicon; Silicon germanium; Stress; $hbox{1}/f$ noise; Contact-etching stop layer (CESL); MOSFET; SiGe channel; reliability;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2010.2073438
Filename
5597915
Link To Document