Title :
A BiCMOS implementation of a 276 MS/s forward equalizer and 200 MS/s FDTS detector
Author :
Harjani, R. ; Barnett, R. ; Butenhoff, M.
Author_Institution :
Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
fDate :
1/1/1998 12:00:00 AM
Abstract :
An analog finite impulse response filter (FIR) and an analog fixed delay tree search (FDTS) tau=l detector suitable for disk drive applications are presented. The FIR uses a rotary architecture with interleaved operation which allows clock rates up to 276 MS/s to be used. The FIR has seven taps, all programmable to six bit weights, and is implemented in fully differential form. The detector operates with clock rates up to 200 MS/s with no code restrictions. It makes use of a reduced minimum mean square error equation set to simplify the detector. Dual feedback filters are also used to shorten the critical path. A seven tap feedback filter is used with six bits of resolution per tap. The FIR consumes 180 mW while the detector uses 270 mW. The die size including all test buffers for the FIR and detector is 5.2 mm2
Keywords :
BiCMOS analogue integrated circuits; FIR filters; circuit feedback; decision feedback equalisers; detector circuits; hard discs; 180 mW; 270 mW; BiCMOS implementation; FDTS detector; analog finite impulse response filter; bit weights; clock rates; disk drive applications; dual feedback filters; fixed delay tree search; forward equalizer; interleaved operation; minimum mean square error equation set; rotary architecture; test buffers; BiCMOS integrated circuits; Clocks; Delay; Detectors; Disk drives; Equalizers; Equations; Feedback; Finite impulse response filter; Mean square error methods;
Journal_Title :
Magnetics, IEEE Transactions on
