SOI for digital CMOS VLSI: design considerations and advances

Author

Chuang, Ching-Te ; Lu, Pong-Fei ; Anderson, Carl J.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

86

Issue

4

fYear

1998

fDate

4/1/1998 12:00:00 AM

Firstpage

689

Lastpage

720

Abstract

This paper reviews the recent advances of silicon-on-insulator (SOI) technology for complementary metal-oxide-semiconductor (CMOS) very-large-scale-integration memory and logic applications. Static random access memories (SRAMs), dynamic random access memories (DRAMs), and digital CMOS logic circuits are considered. Particular emphases are placed on the design issues and advantages resulting from the unique SOI device structure. The impact of floating-body in partially depleted devices on the circuit operation, stability, and functionality are addressed. The use of smart-body contact to improve the power and delay performance is discussed, as are global design issues

Keywords

CMOS digital integrated circuits; VLSI; circuit stability; delays; integrated circuit design; silicon-on-insulator; DRAM; SOI; SRAM; VLSI; circuit stability; delay performance; design considerations; digital CMOS; floating-body; functionality; global design issues; logic circuits; partially depleted devices; power performance; smart-body contact; CMOS logic circuits; CMOS technology; DRAM chips; Delay; Integrated circuit technology; Isolation technology; Large-scale systems; SRAM chips; Silicon on insulator technology; Very large scale integration;

fLanguage

English

Journal_Title

Proceedings of the IEEE

Publisher

ieee

ISSN

0018-9219

Type

jour

DOI

10.1109/5.663545

Filename

663545