DocumentCode
1347249
Title
Parallel architecture modified Booth multiplier
Author
Cooper, A.R.
Author_Institution
STC Technol. Ltd., Harlow, UK
Volume
135
Issue
3
fYear
1988
fDate
6/1/1988 12:00:00 AM
Firstpage
125
Lastpage
128
Abstract
The paper describes a novel implementation of the modified Booth algorithm in which groups of the partial product terms are summed in parallel and these partial results are then combined in a Wallace tree adder array. The final output is formed by an accelerated carry adder. An extension of the scheme from unsigned binary arithmetic to 2´s complement is also described. A 16-bit version of the architecture has been modelled in Pascal and Ella to validate its operation for use in a systolic array DSP chip
Keywords
CMOS integrated circuits; VLSI; digital arithmetic; microprocessor chips; multiplying circuits; parallel architectures; 16 bit; 2´s complement; CMOS; Ella; Pascal; Wallace tree adder array; accelerated carry adder; implementation; modified Booth algorithm; modified Booth multiplier; multiplier architecture; parallel architecture; summed in parallel; systolic array DSP chip; unsigned binary arithmetic;
fLanguage
English
Journal_Title
Electronic Circuits and Systems, IEE Proceedings G
Publisher
iet
ISSN
0143-7089
Type
jour
Filename
6637
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