High-performance digit-serial complex multiplier

Author

Chang, Yun-Nan ; Parhi, Keshab K.

Author_Institution

Dept. of Comput. Sci. & Inf. Eng., Nat. Chung-Cheng Univ., Taiwan

Volume

47

Issue

6

fYear

2000

fDate

6/1/2000 12:00:00 AM

Firstpage

570

Lastpage

572

Abstract

The authors present a fast highly regular digit-serial complex multiplier (CMUL) architecture which is well suited for VLSI implementations. They make two contributions. First, several complex-number representation schemes are discussed. It is shown that the proposed real-imaginary alternate scheme is the best among all representation schemes and the prior designs of CMUL´s based on the radix-(2j) Redundant Complex Number System (RCNS) are not efficient with respect to hardware complexity and processing speed. Second, digit-serial CMUL architectures which can be pipelined at fine-grain level to increase the throughput rate are designed based on the carry-save configuration. The proposed design methodology can also result in low-power dissipation due to the reduced wiring complexity and glitching activity

Keywords

VLSI; integrated logic circuits; low-power electronics; monolithic integrated circuits; multiplying circuits; pipeline arithmetic; VLSI implementations; carry-save configuration; complex-number representation schemes; design methodology; digit-serial complex multiplier; fine-grain level pipelining; glitching activity reduction; hardware complexity; low-power dissipation; processing speed; real-imaginary alternate scheme; throughput rate; wiring complexity reduction; Arithmetic; Convolution; Design methodology; Digital communication; Filtering; Hardware; Signal processing algorithms; Throughput; Very large scale integration; Wiring;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.847078

Filename

847078