Impedance Matching of Traces and Multilayer via Transitions for On-Package Links

Author

Hernandez-Sosa, Gaudencio ; Torres-Torres, Reydezel ; Sanchez, Adán

Author_Institution

Dept. of Elec tronics, Inst. Nac. de Astrofis., Opt. y Electron. (INAOE), Tonanzintla, Mexico

Volume

21

Issue

11

fYear

2011

Firstpage

595

Lastpage

597

Abstract

A method for achieving impedance matching between traces and multilayer via transitions in on-package chip-to-chip links is presented. The method allows determining of the geometry for minimizing the return loss when a signal propagates through the link. For this purpose, analytical equations are derived using a physically-based equivalent circuit to represent the input impedance of multilayer via transitions. S -parameter measurements performed to optimized links using the method demonstrate the usefulness of the proposal.

Keywords

S-parameters; electronics packaging; equivalent circuits; impedance matching; multilayers; S-parameter measurements; analytical equations; impedance matching; multilayer via transitions; on-package chip-to-chip links; physically-based equivalent circuit; return loss; trace via transitions; Capacitance; Impedance; Impedance matching; Integrated circuit modeling; Mathematical model; Nonhomogeneous media; Surface impedance; Impedance matching; return loss; vias;

fLanguage

English

Journal_Title

Microwave and Wireless Components Letters, IEEE

Publisher

ieee

ISSN

1531-1309

Type

jour

DOI

10.1109/LMWC.2011.2167136

Filename

6042347