DocumentCode
1347902
Title
A delay budgeting algorithm ensuring maximum flexibility in placement
Author
Sarrafzadeh, Majid ; Knol, David A. ; Téllez, Gustavo E.
Author_Institution
Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Volume
16
Issue
11
fYear
1997
fDate
11/1/1997 12:00:00 AM
Firstpage
1332
Lastpage
1341
Abstract
In this paper, we present a new, general approach to the problem of computing upper bounds on net delays. The upper bounds on net delays are computed so that timing constraints between input and output signals are satisfied. The set of delay upper bounds is called a delay budget. The objective of this work is to compute a delay budget that will lead to timing feasible circuit placement and routing. In our formulation, we find a delay budget so that the placement phase has “maximum flexibility.” We formulate this problem as a convex programming problem and prove that it has a special structure. We utilize the special structure of the problem to propose an efficient graph-based algorithm. We present experimental results for our algorithms with the MCNC placement benchmarks. Our experiments use budgeting results as net length constraints for the TimberWolf placement program, which we use to evaluate the budgeting algorithms. We obtain an average of 50% reduction in net length constraint violations over the well-known zero-slack algorithm (ZSA). We also study different delay budgeting objective functions, which yield 2× performance improvements without loss of solution quality. Our results and graph-based formulation show that our proposed algorithm is suitable for modern large-scale budgeting problems
Keywords
circuit layout CAD; convex programming; delays; graph theory; integrated circuit layout; network routing; timing; wiring; constraint violations; convex programming problem; delay budgeting algorithm; delay budgeting objective functions; graph-based algorithm; net delays; net length constraints; placement flexibility; solution quality; timing constraints; upper bounds; Algorithm design and analysis; Delay; Integrated circuit yield; Joining processes; Large-scale systems; Performance loss; Routing; Timing; Upper bound; Wire;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.663823
Filename
663823
Link To Document