Author_Institution :
Dept. of Comput. Sci., Illinois Univ., Urbana, IL
Abstract :
The evaluation of advanced routing features must be based on both of costs and benefits. To date, adaptive routers have generally been evaluated on the basis of the achieved network throughput (channel utilization), ignoring the effects of implementation complexity. In this paper, we describe a parameterized cost model for router performance, characterized by two numbers: router delay and flow control time. Grounding the cost model in a 0.8 micron gate array technology, we use it to compare a number of proposed routing algorithms. From these design studies, several insights into the implementation complexity of adaptive routers are clear. First, header update and selection is expensive in adaptive routers, suggesting that absolute addressing should be reconsidered. Second, virtual channels are expensive in terms of latency and cycle time, so decisions to include them to support adaptivity or even virtual lanes should not be taken lightly. Third, requirements of larger crossbars and more complex arbitration cause some increase in the complexity of adaptive routers, but the rate of increase is small. Last, the complexity of adaptive routers significantly increases their setup delay and flow control cycle times, implying that claims of performance advantages in channel utilization and low load latency must be carefully balanced against losses in achievable implementation speed
Keywords :
multiprocessor interconnection networks; network routing; adaptive routing; advanced routing; channel utilization; deadlock prevention; flow control cycle times; gate array; implementation complexity; implementation speed; low load latency; multicomputers; n-cube wormhole routers; parallel computing; router performance; setup delay; Clocks; Concrete; Costs; Delay effects; Grounding; Network topology; Parallel machines; Routing; System recovery; Throughput;