Design and Implementation of a Parallel Turbo-Decoder ASIC for 3GPP-LTE

Author

Studer, Christoph ; Benkeser, Christian ; Belfanti, Sandro ; Huang, Quiting

Author_Institution

Commun. Technol. Lab. (CTL), ETH Zurich, Zurich, Switzerland

Volume

46

Issue

1

fYear

2011

Firstpage

8

Lastpage

17

Abstract

Turbo-decoding for the 3GPP-LTE (Long Term Evolution) wireless communication standard is among the most challenging tasks in terms of computational complexity and power consumption of corresponding cellular devices. This paper addresses design and implementation aspects of parallel turbo-decoders that reach the 326.4 Mb/s LTE peak data-rate using multiple soft-input soft-output decoders that operate in parallel. To highlight the effectiveness of our design-approach, we realized a 3.57 mm² radix-4based 8× parallel turbo-decoder ASIC in 0.13 μm CMOS technology achieving 390 Mb/s. At the more realistic 100 Mb/s LTE milestone targeted by industry today, the turbo-decoder consumes only 69 mW.

Keywords

3G mobile communication; CMOS integrated circuits; Long Term Evolution; application specific integrated circuits; cellular radio; communication complexity; parallel processing; turbo codes; 3GPP-LTE; CMOS technology; LTE wireless communication; Long Term Evolution; bit rate 390 Mbit/s; cellular device; computational complexity; parallel turbo-decoder ASIC; power 69 mW; power consumption; size 0.13 mum; soft-input soft-output decoder; turbo decoding; Decoding; Memory management; Multiaccess communication; Random access memory; Systematics; Throughput; 3G mobile communication; ASIC implementation; LTE; low-power; parallel turbo-decoder; radix-4;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2010.2075390

Filename

5599882