Title :
A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm
Author :
Lai, Yeong-Kang ; Chen, Liang-Gee
Author_Institution :
Dept. of Electron. Eng., Chang Gung Univ., Taiwan
fDate :
4/1/1998 12:00:00 AM
Abstract :
This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse for full-search blockmatching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates
Keywords :
digital signal processing chips; image matching; motion estimation; parallel processing; search problems; shift registers; 1D processing element array; 2D data-reuse; VLSI; block sizes; chips; data-interlacing architecture; data-interlacing shift-register arrays; full-search block-matching algorithm; hardware utilization; high throughput rate; memory access reduction; motion estimation; pin counts; pixel rates; search ranges; Computer architecture; Hardware; Motion estimation; Parallel processing; Shift registers; Systolic arrays; Throughput; Two dimensional displays; Very large scale integration; Video coding;
Journal_Title :
Circuits and Systems for Video Technology, IEEE Transactions on
