Energy and Spatial Distributions of Electron Traps Throughout $\hbox {SiO}_{2}/\hbox {Al}_{2}\hbox {O}_{3}$ Stacks as the IPD in Flash Memory Application

SiO₂/high-¿ dielectric stacks will soon replace the conventional SiO₂-based dielectric stacks in flash memory cells, as the thickness of SiO₂ -based stacks is approaching its fundamental limit. The electron trap density in high-¿ layers is orders of magnitude higher than that in SiO₂, which may introduce excessive leakage via trap-assisted tunneling current and become the limiting factor for the retention of memory cells. Understanding the properties of electron traps throughout the dielectric stack is essential for estimating the leakage current and for selecting materials and processes in order to reduce the leakage. However, detailed information on trap properties in the bulk of high-¿ layers is still missing. A recently developed two-pulse C-V measurement technique is used in this paper to investigate the energy and spatial distribution of electron traps throughout the SiO₂/Al₂O₃ dielectric stacks. Four energy regions of electron traps have been observed. The shallower traps mainly above the Si conduction band bottom E _CB are found distributed across the Al₂O₃ layer. A narrow band of traps below Si E _CB with a bandwidth of about 0.1 eV can be observed near the SiO₂/Al₂O₃ interface. Traps in the midlevel region corresponding to Si bandgap and traps in the deeper energy region mainly below Si valence band top are also observed. The postdeposition annealing in N₂ has different impacts on the electron traps in different energy regions.