Title :
A heuristic algorithm for via minimization in VLSI channel routing
Author :
Das, Biswajit ; Mahato, Ajoy Kumar ; Khan, Ajoy Kumar
Author_Institution :
Dept. of Comput. Sci. & Eng., North Eastern Regional Inst. of Sci. & Technol., Nirjuli, India
Abstract :
We know that via minimization is a very important problem in channel routing. The main aim of via minimization is to improve the circuit performance and productivity, to reduce the completion rate of routing and also to fabricate integrated circuit correctly. In this paper, we are using a heuristic algorithm for solving via minimization problem in VLSI channel routing with movable terminal. Here we concentrate on how fast we find out maximum independent set from the net intersection graph. That is why here we use heuristic technique to find the maximum independent set of a graph with polynomial time complexity. Next, we show how to use that maximum independent set to solve the via minimization problem using an example. Then, we show the experimental results and hardcopy solutions of some channel instances to prove the efficiency of this approach.
Keywords :
VLSI; integrated circuit manufacture; VLSI; channel routing; heuristic algorithm; integrated circuit; polynomial time complexity; Algorithm design and analysis; Design automation; Heuristic algorithms; Minimization; Routing; Very large scale integration; Wires; Channel routing; Heuristic algorithm; Maximum independent set; Movable terminal; Net intersection graph; Via;
Conference_Titel :
Automation, Control, Energy and Systems (ACES), 2014 First International Conference on
Conference_Location :
Hooghy
Print_ISBN :
978-1-4799-3893-3
DOI :
10.1109/ACES.2014.6807986