2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing

Author

Ide, Nobuhiro ; Hirano, Masashi ; Endo, Yukio ; Yoshioka, Shin Ichi ; Murakami, Hiroaki ; Kunimatsu, Atsushi ; Sato, Toshinori ; Kamei, Takayuki ; Okada, Toyoshi ; Suzuoki, Masakazu

Author_Institution

Syst. LSI Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan

Volume

35

Issue

7

fYear

2000

fDate

7/1/2000 12:00:00 AM

Firstpage

1025

Lastpage

1033

Abstract

A vector unit for high-performance three-dimensional graphics computing has been developed. We implement four floating-point multiply-accumulate units, which execute multiply-add operations with one throughput; one floating-point divide/square root unit, which executes division and square-root operations with six cycles at 300 MHz; and one vector general-purpose register file, which has 128 bits/spl times/32 words. The parallel execution of all units delivers a peak performance of 2.44 GFLOPS at 300 MHz.

Keywords

computer graphic equipment; digital signal processing chips; floating point arithmetic; parallel architectures; vector processor systems; 128 bit; 2.44 GFLOPS; 300 MHz; 3D graphics computing; division operations; floating-point divide/square root unit; floating-point vector-processing unit; multiply-add operations; parallel execution; square-root operations; vector general-purpose register file; Animation; CMOS technology; Computational geometry; Computer architecture; Computer graphics; Frequency; Pipeline processing; Process design; Registers; Throughput;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.848212

Filename

848212