New improved high speed low power double tail comparator design for 2.5 GHz input signal

Modern communication and signal processing is dependent on the high speed and low power consumption of the Analog-to-Digital converters (ADC) to a very large extent. Comparator is the basic building block of the ADCs which compares the two set of variables and change the input analog signal in digital. In this paper a new design of double tail comparator is proposed for high frequency of data conversion and is compared with the best available recently proposed double tail comparator design in term of area on chip power utilization, delay consideration and PDP. For a frequency higher than 350 MHz the power consumption is less for the proposed double tail comparator design, which keeps on getting better with every rising frequency. The maximum frequency of operation is also increased from 1.7 GHz to 2.5 GHz along with lesser delay which is significant considering the need of high speed devices. Apart from the proposed DT comparator shows an improvement of 23.57% in terms of area than the previous best design.