• DocumentCode
    1351241
  • Title

    MVP: Minimum-Violations Partitioning for Reducing Capture Power in At-Speed Delay-Fault Testing

  • Author

    Chen, Zhen ; Chakrabarty, Krishnendu ; Xiang, Dong

  • Author_Institution
    Dept. of Comput. Sci. & Technol ogy, Tsinghua Univ., Beijing, China
  • Volume
    30
  • Issue
    11
  • fYear
    2011
  • Firstpage
    1762
  • Lastpage
    1767
  • Abstract
    Scan shift power can be reduced by activating only a subset of scan cells in each shift cycle. In contrast to shift power reduction, the use of only a subset of scan cells to capture responses in a cycle may cause capture violations, thereby leading to fault coverage loss. In order to restore the original fault coverage, new test patterns must be generated, leading to higher test-data volume. In this paper, we propose minimum-violations partitioning, a scan-cell clustering method that can support multiple capture cycles in delay testing without increasing test-data volume. This method is based on an integer linear programming model and it can cluster the scan flip-flops into balanced parts with minimum capture violations. Based on this approach, hierarchical partitioning is proposed to make the partitioning method routing-aware. Experimental results on ISCAS´89 and IWLS´05 benchmark circuits demonstrate the effectiveness of our method.
  • Keywords
    automatic test pattern generation; flip-flops; integer programming; linear programming; logic testing; low-power electronics; pattern clustering; ISCAS´89 benchmark circuit; IWLS´05 benchmark circuit; at-speed delay-fault testing; capture power reduction; delay testing; fault coverage loss; hierarchical partitioning; integer linear programming model; minimum-violations partitioning; routing awareness; scan flip-flop clustering; scan shift power reduction; scan-cell clustering method; test pattern generation; test-data volume; Circuit faults; Delay testing; Integrated circuit interconnections; Integrated circuit modeling; Low power electronics; Capture power; delay testing; low-power testing; minimum-violations partitioning;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2011.2162237
  • Filename
    6046167