DocumentCode
1351296
Title
A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives
Author
Liao, Kuan-Yu ; Chang, Chia-Yuan ; Li, James Chien-Mo
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
30
Issue
11
fYear
2011
Firstpage
1767
Lastpage
1772
Abstract
This paper proposes a bit-level parallel ATPG algorithm (SWK) that generates multiple test patterns at a time. This algorithm converts decisions into bitwise logic operation so that W (CPU word size) test patterns are searched independently. Multiple objectives for different quality metrics can therefore be achieved in a single test generation process. Experimental results on ISCAS´89 and IWLS´05 benchmark circuits show that SWK test sets are better in many quality metrics than traditional 50-detect test sets, while the length of the former is shorter. Also, patterns selected from large N-detect pattern pool cannot achieve the same or higher quality than patterns generated by SWK.
Keywords
automatic test pattern generation; logic testing; ISCAS´89 benchmark circuit; IWLS´05 benchmark circuit; N-detect pattern pool; SWK test set; bit-level parallel ATPG algorithm; bitwise logic operation; multiple quality objective; multiple test pattern generation; quality metric; split-into-W-clone test set; Automatic test pattern generation; Benchmark testing; Circuit faults; Logic gates; Mathematical model; Parallel processing; Testing; Bitwise parallel; test pattern generation; test quality;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2011.2157693
Filename
6046178
Link To Document