DocumentCode
1351324
Title
Unified 2-D X-Alignment for Improving the Observability of Response Compactors
Author
Sinanoglu, Ozgur ; Almukhaizim, Sobeeh
Author_Institution
Dept. of Comput. Eng., New York Univ., Abu Dhabi, Saudi Arabia
Volume
30
Issue
11
fYear
2011
Firstpage
1744
Lastpage
1757
Abstract
Despite the advantages of performing response compaction in integrated-circuit testing, unknown response bits (x´s) inevitably reflect into loss in test quality. The distribution of these x´s within the captured response, which varies for each test pattern, directly impacts the number of scan cells observed through the response compactor. In this paper, we propose a unified 2-D x-alignment technique in order to judiciously manipulate the distribution of x´s in the test response prior to its compaction. The controlled response manipulation is performed on a per pattern basis, in the form of scan chain delay and intra-slice rotate operations, and with the objective that x´s are aligned within as few scan slices and chains as possible. Consequently, a larger number of scan cells are observed after compaction for any test pattern. In an effort to tackle the unified 2-D x-alignment problem and to achieve maximum overall observability, we first decipher the interaction between 1-D x-alignment operations, and formulate 1-D and 2-D x-alignment operations all as maximum satisfiability (MAX-SAT) problems; a weighted MAX-SAT formulation is necessitated in the 2-D case to identify the best possible 2-D x-alignment, which may differ from back to back application of the individual best possible 1-D alignments in two dimensions. The proposed technique is test set independent, leading to a generic, simple, and cost-effective hardware implementation. While we show in this paper that x-alignment improves horizontal and vertical compactors, covering a wide spectrum of compactors, it is expected to improve other types of compactors as well by manipulating the x-distribution properly.
Keywords
VLSI; integrated circuit testing; 1D x-alignment operations; controlled response manipulation; integrated-circuit testing; response compactors; scan chain delay; test pattern; test quality; unified 2D x-alignment technique; very large-scale integrated circuit; Adaptation models; Circuit faults; Data compression; Design for quality; Two dimensional displays; Design for testability; satisfiability; scan-based test; test data compression; testing;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2011.2160175
Filename
6046182
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