Parameters optimization of Lateral impact ionization MOS (LIMOS)

Impact Ionization MOSFET (IMOS), has emerged to combat one of the most critical and fundamental problem of sub-threshold slope (SS) which cannot be lower than 60mV/decade at room temperature for conventional MOSFET, as conventional MOSFET works on the principle of diffusion of charge carrier for the current flow in the device. Whereas, the IMOS devices work on the principle of avalanche breakdown to switch from the `OFF´ state to `ON´ state. In this paper, we have optimized the device performance of the Lateral impact ionization MOSFET (LIMOS) by varying the device dimensional parameters, such as gate length L_g, intrinsic length L_in, gate dielectric thickness t_ox and biasing voltages V_g and V_s. Simulation results claims that the ratio of L_g/L_in has to be properly tuned for the optimum device performance. If this ratio approaches to one LIMOS performance are optimized, whereas if it is very higher than one it behaves as Tunnel Field Effect Transistor (TFET) and if it is very less than one it effectively behaves as gated PIN diode. Simulation results show the sub-threshold slope SS to be 1.373mV/dec for our optimized LIMOS. Considerable improvement in other device performance parameters namely I_on, I_off, I_on/I_off ratio, threshold voltage V _th, breakdown voltage V_br, drain induced current enhancement DICE, and gate induced barrier lowering GIBL has been reported.